A computer processor (processing unit) generally comprises a control unit, which directs the operation of the system, and one or more arithmetic execution units, which perform computational operations. The execution units can include an arithmetic logic unit (ALU) for integer operations and a multiply accumulate unit (MAC) for floating point operations. The overall design of a processor involves the selection of a register set(s), communication passages between these registers, and a means of directing and controlling how these operate. Normally, a processor is directed by a program, which includes a series of instructions that are kept in a main memory. Each instruction is a group of bits, usually one or more words in length, specifying an operation to be carried out by the processor. In general, the basic cycle of a processor comprises the following steps: (a) fetch an instruction from memory into an instruction register; (b) decode the instruction (i.e., determine what it indicates should be done; each instruction indicates an operation to be performed and the data to which the operation should be applied); (c) carry out the operation specified by the instruction; and (d) determine where the next instruction is located. Normally, the next instruction is the one immediately following the current one.
However, in high performance processors, such as superscalar processors where two or more scalar operations are performed in parallel, the processor may be designed to perform instructions that are out of order, or in an order that is not consistent with that defined by the software driving the processor. In these systems, instructions are executed when they can be executed, as opposed to when they appear in the sequence defined by the program. Moreover, after execution of out of order instructions, the results are ultimately reordered to correspond with the instruction order, prior to passing the results back to the program.
Out of order execution of instructions poses peculiar obstacles from a design perspective. One such obstacle involves tracking instruction dependencies. An instruction, called the "dependent" instruction, is dependent upon another instruction, called the "producer" instruction, when the dependent instruction operates upon an operand or result that is produced from the producer instruction.
As an example, consider an addition operation that has a carry borrow (cb) value that must be transferred from one instruction to another. In this regard, suppose a 64 bit addition is to be accomplished, and the computer is a 32 bit machine. In this scenario, a cb bit must be transferred from the first operation and applied to the second operation.
As another example, consider a shift amount register (sar) operation that involves a control register. A dependent instruction must wait until its producer instruction manipulates the register value.
Generally, dependent instructions are placed after their producer instructions in program order, and therefore, in a typical processor that executes instructions in order, the dependent instructions are executed after their producer instructions, and no execution ordering problems arise. However, in a processor that executes instructions out of order, unless safeguards are implemented, it is possible that a dependent instruction may be executed prior to the producer instruction from which it depends. Accordingly, in some designs of out of order processors, dependency operands need to be tracked.
Another issue that is dealt with in out of order processor designs involves the generation and tracking of trap information. A "trap" is an indicator that is generated to indicate when a special process should be executed by the processor. Traps are well known in the art. The industry standard Precision Architecture for RISC processors defines numerous trap types. Examples are as follows: an "overflow trap," which is initiated by an instruction when a result is too large for the result register and a "privileged operation trap," which is initiated by the operating system when other software, such as application software, attempts to execute an instruction that can only be executed by the operating system. For more information regarding traps, see the widely available publication entitled, "PA RISC 2.0 Architecture," Prentice Hall (1996) or its corresponding predecessor publications regarding Reduced Instruction Set Computer (RISC) architectures.
While a processor executes instructions out of order, the trap and dependency information is stored until the processor can ultimately act upon the information. Needless to say, storage requires memory and space, both of which are expensive commodities in processors and should be minimized in processor designs. Accordingly, a heretofore unaddressed need exists in the industry for systems and methods for reducing the amount of storage necessary for maintaining trap and dependency information in a processor that executes instructions out of order.